1. Field of the Invention
This invention relates to a high-voltage input tolerant receiver, and more particularly, to a high-voltage input tolerant receiver, which receives an external signal varying between ground and a high voltage limit of the internal elements of the receiver, and outputs an internal signal varying between ground and just below the high voltage limit of the internal elements of the receiver.
2. Background of the Invention
There is a high-voltage input tolerant receiver as shown in FIG. 3 used as an interface from a 5 V driving element to 3.3 V driving element. Referring to FIG. 3, a conventional high-voltage input tolerant receiver 100 includes a PAD 2, a clamp circuit 31, a level keeper 60, a buffer circuit 15, and a hysteresis circuit 5. The clamp circuit 31, connected between the output node of the PAD 2 and the input node of an inverter IV1 in the buffer circuit 15, has an n-channel MOS transistor N1 with its gate connected to a 3.3 V power-supply potential node 10. The level keeper 60 has a p-channel MOS transistor P9. The p-channel MOS transistor P9, connected between the 3.3 V power-supply potential node 10 and the input node of the inverter IV1, receives at its gate an output signal from the inverter IV1. In the buffer circuit 15, inverters IV1 to IV4 are connected in series so that an internal signal φB will be output from the inverter IV4.
When an external signal φC input from PAD 2 is less than 3.3 V−VthN1, the clamp circuit 31 outputs an intermediate signal φD equivalent to the external signal φC, where VthN1 is a threshold voltage of the n-channel MOS transistor N1. Conversely, when the external signal φC exceeds 3.3 V−VthN1, the clamp circuit 31 clamps the intermediate signal φD to 3.3 V−VthN1, which prevents the internal elements of the high-voltage input tolerant receiver 100 from being damaged or destroyed by high voltage signals.
When the intermediate signal φD is clamped to 3.3 V−VthN1, the p-channel MOS transistor P9 in the level keeper 60 is turned on, pulling the intermediate signal φD input to the inverter IV1 up to 3.3 V, which prevents shoot-through current from flowing into the inverter IV1.
FIG. 4 shows variations of the intermediate signal φD and internal signal φB, and variations of current I1 flowing from the level keeper 60 as the external signal φC varies from 0 V to 5.5 V.
Referring to FIG. 4, the external signal φC varies from 0 V to 3.3 V during the period from time t10 to time t20. During this period, the intermediate signal φD output from the clamp circuit 31 is equivalent to the external signal φC. After time t20, the external signal φC exceeds 3.3 V−VthN1, and the clamp circuit 31 clamps the intermediate signal φD to 3.3 V−VthN1. Since the potential difference between the clamped intermediate signal φD and the ground potential GND exceeds a threshold voltage V thN2 of an n-channel MOS transistor N2, current flows into the n-channel MOS transistor N2 in the inverter IV1 to turn on the n-channel MOS transistor N2, allowing the inverter IV1 to output a 0 V signal. At this time, since the potential difference between the 0 V output signal from the inverter IV1 and the 3.3 V power-supply potential exceeds a threshold voltage VthP9 of the p-channel MOS transistor P9, the p-channel MOS transistor P9 is turned on. As a result, the level keeper 60 pulls up the intermediate signal φD, and at time t30, the intermediate signal φD becomes 3.3 V. After the intermediate signal φD is pulled up to 3.3 V, only the n-channel MOS transistor N2 in the inverter IV1 is in operation, thereby preventing the shoot-through current.
Then, after time t40, the level of the external signal φC is reduced, and at time t50, although it becomes lower than that of the intermediate signal φD, since the level keeper 60 is active, the intermediate signal φD is maintained at 3.3 V. Ultimately, at time t60, at which point the level keeper 60 goes beyond being tolerant of the voltage drop of the external signal φC, the p-channel MOS transistor P9 is turned off, and the voltage level of the intermediate signal φD becomes equal to that of the external signal φC just after time t60.
The high-voltage input tolerant receiver 100 uses the clamp circuit 31 to protect the 3.3 V driving elements and the level keeper 60 to prevent the occurrence of shoot-through current in the inverter IV1. Such a high-voltage input tolerant receiver 100, however, causes the following problems.
(1) Analog signals are distorted in the high-voltage input tolerant receiver.
In the high-voltage input tolerant receiver 100, when the external signal φC is higher than 3.3 V−VthN1, the intermediate signal φD is clamped to 3.3 V−VthN1. In this case, the intermediate signal φD does not accord with the external signal φC, creating distortion. When the external signal φC is a digital signal distortion is not a concern, but for analog signals the distortion can be significant.
(2) The reset function does not work in a reset circuit using the high-voltage input tolerant receiver.
In a reset circuit 200 shown in FIG. 5, when a driver 300 has low drive power, even if a logic Low level signal is output from the driver 300, it will not become a perfect 0 V signal. Since the high-voltage input tolerant receiver 100 has the hysteresis circuit 5, the high-voltage input tolerant receiver 100 will evaluate whether any input signal is at a logic high level unless the input signal into the high-voltage input tolerant receiver 100, that is, the external signal φC, becomes equal to or lower than a logic low level threshold voltage Vil interpreted by the hysteresis circuit 5. As a result, the level keeper 60 continues to operate so that the high-voltage input tolerant receiver 100 will continuously output the logic high signal without being reset. This problem arises when sink current flowing into the driver 300 is smaller than the sum of current 12 flowing into a pull-up resistor R100 and current I1 flowing from the level keeper 60 in the high-voltage input tolerant receiver 100.
(3) Unnecessary current I1 flows from the level keeper 60.
Current I1 flows from the level keeper 60 to the outside during the period from time t20 to time t30 and after time t60 in FIG. 4 and causes unnecessary power consumption.
Japanese Patent Laid-Open No. 2000-278113 discloses an example of an input/output circuit with the above described deficiencies with respect to distortion of analog signals and power dissipation.